The Semiconductor Capex Machine
The semiconductor capital expenditure cycle is defined by three interdependent variables that historically move together but with different phase lags: hyperscaler AI infrastructure demand, foundry utilisation and equipment lead times. When all three are reinforcing, the cycle appears infinite and consensus extrapolates the trend. When any one turns, the cliff appears surprisingly quickly.
Hyperscaler AI infrastructure demand has been the cycle driver since 2022. Microsoft, Amazon, Google and Meta collectively spent approximately USD 230 billion on capital expenditure in 2025, a significant portion of which flowed into AI accelerator chips (primarily NVIDIA and AMD GPUs), custom silicon (Google TPUs, Amazon Trainium) and the power and networking infrastructure to support AI data centres. The aggregate demand signal from the hyperscaler tier is enormous and has been the foundation of the bull thesis for TSMC, NVIDIA, ASML and the broader semiconductor equipment complex.
The problem is that hyperscaler capex is not smooth. It is lumpy, driven by strategic decisions that are made in investment committees, not by marginal demand signals. And the decisions that drove the 2023 to 2025 wave of investment were made in response to a specific demand environment (the initial ChatGPT wave and the first wave of enterprise AI deployment) that is now maturing.
The Demand Model Problem
The current semiconductor capex cycle is built on projections of AI compute demand that the desk believes are structurally overestimated in the consensus, not because AI is a bubble (it is not) but because the mapping from AI adoption to chip demand involves several compounding assumptions, each of which is optimistic in the consensus.
First, adoption pace: the consensus assumes enterprise AI adoption at the rate demonstrated by early adopters. The actual diffusion rate for a technology requiring significant workflow re-engineering, data infrastructure and talent is substantially slower for the median enterprise than for the early-adopter tier.
Second, inference versus training: the consensus chip demand model is heavily weighted toward training compute, which is more chip-intensive. The shift from training-heavy deployments to inference-heavy production use tends to favour different chips (smaller, more efficient inference chips versus large training clusters), which changes the revenue profile of the semiconductor supply chain.
Third, energy and power constraints: data centre power availability is becoming a genuine bottleneck for AI infrastructure expansion. Hyperscalers face permitting, grid connection and equipment delivery delays that are creating a gap between announced capex plans and actual deployed infrastructure. This slows the translation of capex intention into chip orders.
Track hyperscaler guidance revisions in their quarterly earnings calls. A revision from 'we plan to spend substantially more on AI infrastructure in 2026' to 'we are pausing to assess returns' would be the first cut in the cycle thesis.
Foundry Utilisation And The Inventory Build
TSMC is the foundry for both NVIDIA's AI chips and Apple's consumer chips, which makes its utilisation data the most comprehensive leading indicator for the cycle. TSMC's advanced node (3nm and 5nm) utilisation has been at or above 95 percent since mid-2024, which is why TSMC has been pricing at premium to normal cycle levels.
Legacy node utilisation is more mixed. TSMC's 28nm and above nodes are running at approximately 70 to 80 percent, below the 85 to 90 percent level required for peak pricing power. Legacy nodes serve consumer electronics, automotive and industrial markets that have been in different phases of their own inventory cycles.
The inventory build risk is concentrated at the memory tier. DRAM and NAND capacity expansions by Samsung, Micron and SK Hynix in 2024 to 2025 are coming online in 2026. If AI demand growth decelerates even modestly from current consensus, the resulting memory inventory build could be rapid and would flow upstream to TSMC through reduced orders from NVIDIA and other AI chip designers.
Equipment Lead Times
ASML's extreme ultraviolet (EUV) lithography machines are the most critical and longest lead-time equipment in the semiconductor capital expenditure cycle. ASML books orders 12 to 18 months before delivery; its backlog provides perhaps the best public visibility into the 2026 to 2027 foundry capex intentions.
ASML's order intake in Q4 2025 showed the first quarter-on-quarter decline in 18 months. This is not yet a cliff indicator (it could represent a normal booking pattern pause), but it deserves monitoring. If the Q1 2026 order intake also declines, the pattern would suggest that foundries are beginning to modulate their EUV investments, which would be a leading indicator for the cliff that consensus is not pricing.
Positioning
The desk distinguishes three tiers of cycle sensitivity.
Tier 1 (high sensitivity): semiconductor equipment companies (ASML, Applied Materials, Lam Research) and memory manufacturers (Samsung, Micron). These are the first to feel cycle turns in both directions.
Tier 2 (medium sensitivity): leading-edge foundries (TSMC). Protected by advanced node concentration of AI demand but not immune to a significant AI capex pause.
Tier 3 (lower sensitivity): fabless chip designers with diversified end markets (Broadcom, Marvell) and companies with long customer commitment cycles.